1. Field of the Invention
The present invention relates to a clock signal extracting circuit and more particularly to the clock signal extracting circuit used for a parallel digital interface. As the parallel digital interface, there are an interface between LSI (Large Scale Integrated) circuits on a same substrate, an interface between substrates, an interface between apparatuses and a like.
2. Description of the Related Art
In a parallel digital interface, a clock signal synchronizing operation is applied to plural inputted bit signals in order to compensate a skew caused by a delay difference in a transmission line. A clock signal extracting circuit for generating a clock signal used for this synchronizing operation, as shown in FIG. 9, generally selects a bit signal among plural inputted bit signals and extracts a clock signal based on a selected clock signal.
That is, as shown in FIG. 9, the clock signal extracting circuit includes a phase comparator 902, a charge pump 903, a loop filter 904 and a voltage control oscillator 905 and generates a clock signal 909 based on, for example, an N-th data bit signal 908-N inputted from a N-th data bit signal terminal 901-N among data bit signals inputted from a first data bit signal input terminal 901-1 through the N-th data bit signal input terminal 901-N.
A D-type flip-flop circuit 906-1 through a D-type flip-flop circuit 906-N synchronize an input signal 908-1 through the input signal 908-N by the clock signal 909 and output synchronized signals to a data bit signal output terminal 907-1 through an N-th data bit signal output terminal 907-N. Signals outputted from a first data bit signal output terminal 907-1 through an N-th data bit signal output terminal 907-N are inputted into a rear-stage system.
As shown in FIG. 10, when a clock signal is extracted from only the third data bit signal 908-3 by the clock signal extracting circuit shown in FIG. 9, as indicated by a waveform 405, the extracting clock signal rises at a middle point T21 between adjacent change points of the third data bit signal 908-3. In this extracting clock signal, for example, when retiming is applied to the data bit signal 908-1, a delay of the data bit signal 908-1 displaces largely as to the third data bit signal 908-3, therefore, a time margin of this retiming becomes small.
Therefore, in the parallel digital interface using the conventional signal extracting circuit, there is a problem in that a retiming margin decreases when skews exist among plural bits. Recently, since signals are transmitted via the parallel digital interface at higher and higher speed, it is required that the retiming margin is prevented from decreasing in the parallel digital interface.
In view of the above, it is an object of the present invention to provide a clock signal extracting circuit capable of preventing a retiming margin from decreasing in a parallel digital interface.
According to a first aspect of the present invention there is provided a clock signal extracting circuit for extracting a clock signal from N-pieces of data bit signals, where the N is an integer of two or more, the clock signal extracting circuit including:
N-pieces of phase comparators, each of which compares a phase of each of the data bit signals with a phase of an extracted clock signal and generates a phase difference signal in accordance with a compared result;
a circuit for averaging N-pieces of the phase difference signals and for generating a control voltage; and
a voltage control oscillator for generating the extracted clock signal of a frequency in accordance with the control voltage.
According to a second aspect of the present invention there is provided a clock signal extracting circuit for extracting a clock signal from N-pieces of data bit signals, where the N is an integer of two or more, the clock signal extracting circuit including:
N-pieces of phase comparators, each of which compares a phase of each of the data bit signals with a phase of an extracted clock signal and generates a phase difference signal in accordance with a compared result;
a circuit for generating a control voltage based on a phase difference signal indicating a maximum phase difference and a phase difference signal indicating a minimum phase difference among N-pieces of the phase difference signals; and
a voltage control oscillator for generating the extracted clock signal of a frequency in accordance with the control voltage.
According to a third aspect of the present invention there is provided a clock signal extracting circuit extracting a clock signal from N-pieces of data bit signals, where the N is an integer of two or more, the clock signal extracting circuit including:
N-pieces of phase comparators, each of which compares a phase of each of the data bit signals with a phase of an extracted clock signal and generates a up-signal and a down-signal in accordance with a compared result;
N-pieces of charge pumps, each of which generates a current in accordance with the up-signal and the down-signal inputted from each of the phase comparators;
an adder for adding the currents generated by the N-pieces of charge pumps;
a loop filter for generating a control voltage in accordance with an added current by the adder; and
a voltage control oscillator for generating the extracted clock signal of a frequency in accordance with the control voltage.
According to a fourth aspect of the present invention there is provided a clock signal extracting circuit extracting a clock signal from N-pieces of data bit signals, where the N is an integer of two or more, the clock signal extracting circuit including:
N-pieces of phase comparators, each of which compares a phase of each of the data bit signals with a phase of an extracted clock signal and generates an up-signal and a down-signal in accordance with a compared result;
a maximum up-signal selecting circuit for selecting an up-signal indicating a maximum phase difference among the N-pieces of up-signals;
a minimum up-signal selecting circuit for selecting an up-signal indicating a minimum phase difference among N-pieces of up-signals;
a maximum down-signal selecting circuit for selecting a down-signal indicating a maximum phase difference among N-pieces of down-signals;
a minimum down-signal selecting circuit for selecting a down-signal indicating a minimum phase difference among N-pieces of down-signals;
a first charge pump for generating a current in accordance with the up-signal indicating the maximum phase difference and the down-signal indicating the maximum phase difference;
a second charge pump for generating a current in accordance with the up-signal indicating the minimum phase difference and the down-signal indicating the minimum phase difference;
an adder for adding the current generated by the first charge pump and the current generated by the second charge pump;
a loop filter for generating a control voltage in accordance with an added current by the adder; and
a voltage control oscillator for generating the extracted clock signal of a frequency in accordance with the control voltage.
According to a fifth aspect of the present invention there is provided a clock signal extracting circuit extracting a clock signal from N-pieces of data bit signals, where the N is an integer of two or more, the clock signal extracting circuit including:
N-pieces of phase comparators, each of which compares a phase of each of the data bit signals with a phase of an extracted clock signal and generates an up-signal and a down-signal in accordance with a compared result;
a maximum up-signal selecting circuit for selecting an up-signal indicating a maximum phase difference among N-pieces of up-signals;
a minimum up-signal selecting circuit for selecting an up-signal indicating a minimum phase difference among the N-pieces of up-signals;
a first charge pump for generating a current in accordance with the up-signals indicating the maximum phase difference and one of N-pieces of the down-signals;
a second charge pump for generating a current in accordance with the up-signal indicating the minimum phase difference and one of N-pieces of the down-signals;
an adder for adding the current generated by the first charge pump and the current generated by the second charge pump;
a loop filter for generating a control voltage in accordance with an added current by the adder; and
a voltage control oscillator for generating the extracted clock signal of a frequency in accordance with the control voltage.
According to a sixth aspect of the present invention there is provided a parallel digital interface including:
a clock signal extracting circuit including: N-pieces of phase comparators, where N is an integer of two or more, each of which compares a phase of each of the data bit signals with a phase of an extracted clock signal and generates a phase difference signal in accordance with a compared result; a circuit for averaging N-pieces of the phase difference signals and for generating a control voltage; and a voltage control oscillator for generating the extracted clock signal of a frequency in accordance with the control voltage; and
N-pieces of flip-flop circuits, each of which synchronizes each of the data bit signals with the extracted signal.
According to a seventh aspect of the present invention there is provided a clock signal extracting method of extracting a clock signal from N-pieces of data bit signals, where the N is an integer of two or more, the clock signal extracting method including:
a step of comparing a phase of each of the data bit signals with a phase of an extracted clock signal and of generating N-pieces of phase difference signals in accordance with a compared result;
a step of averaging N-pieces of the phase difference signals and of generating a control voltage; and
a step of generating the extracted clock signal of a frequency in accordance with the control voltage.
According to an eighth aspect of the present invention there is provided a clock signal extracting method of extracting a clock signal from N-pieces of data bit signals, where the N is an integer of two or more, the clock signal extracting method including:
a step of comparing a phase of each of the data bit signals with a phase of an extracted clock signal and of generating N-pieces of phase difference signals in accordance with a compared result;
a step for generating a control voltage based on a phase difference signal indicating a maximum phase difference and a phase difference signal indicating a minimum phase difference among the N-pieces of phase difference signals; and a step of generating the extracted clock signal of a frequency in accordance with the control voltage.
According to a ninth aspect of the present invention there is provided a synchronizing method for a parallel data bit signal including:
a step of comparing a phase of each of the data bit signals with a phase of an extracted clock signal and of generating N-pieces of phase difference signals in accordance with a compared result, where N is an integer of two or more;
a step of averaging N pieces of the phase difference signals and of generating a control voltage;
a step of generating the extracted clock signal of a frequency in accordance with the control voltage; and
a step of synchronizing the N-pieces of data bit signals by the extracted signal.
According to a tenth aspect of the present invention there is provided a clock signal extracting method of extracting a clock signal from N-pieces of data bit signals, where the N is an integer of two or more, the clock signal extracting method including:
a step of comparing a phase of each of the data bit signals with a phase of an extracted clock signal and of generating N-pieces of phase difference signals in accordance with a compared result;
a step for generating a control voltage based on a phase difference signal indicating a maximum phase difference and a phase difference signal indicating a minimum phase difference among the N-pieces of phase difference signals; a step of generating the extracted clock signal of a frequency in accordance with the control voltage; and
a step of synchronizing the N-pieces of data bit signals by the extracted signal.
With the above configurations, in the clock signal extracting circuit generating a clock signal used for retiming and synchronization of plural data bit signals, phase comparator and charge pump circuits are arranged for each data bit signal and outputs from the phase comparator and the charge pump circuits are added and averaged, therefore, a whole retiming margin of plural bits can be increased.
Also, an extracting clock signal is controlled so as to rise at a middle timing between a middle timing value between change timings which are adjacent to each other in a data bit signal of which a change timing is fastest and a middle timing value between change timings which are adjacent to each other in a data bit signal of which a change timing is slowest. Therefore, though there is a deviation of skew among data bit signals, the extracting clock signal does not be displaced. Therefore, in view of all data bit signals, though there is a deviation of skew among data bit signals, it is controlled so as to increase a retiming margin.
Furthermore, in the clock signal extracting circuit, the voltage control oscillator and the loop circuit occupying most of a circuit scale and a power consumption are used commonly, therefore, it is possible to prevent the circuit scale and the power consumption from increasing.